The present invention relates to demultiplexing digital data from multiple input channels, and more particularly for demultiplexing digital data in a non-standard mode that is not a factor of two, such as a 3× mode.
Measurement instruments, such as logic analyzers, have standard demultiplex modes, such as 2× and 4× (factors of two) modes for multiple input channels. The 2× demultiplex mode uses only one-half of the instrument input channels, but doubles the speed and memory length of data acquisition. The 4× mode uses only one-quarter of the instrument input channels, but gets four times the speed and memory depth. These modes allow the measurement instruments to operate faster without increasing system and memory bandwidth.
However sometimes a system under test (SUT) is too fast for the 2× mode and too wide for the 4× mode, but has a bandwidth that is less than that of the measurement instrument. For example if a logic analyzer has 288 input data channels with an 800 Mb/s system clock, the logic analyzer bandwidth is 230 Gb/s. In 2× mode there are 144 input data channels with an equivalent data rate of 1.6 Gb/s, while in the 4× mode there are 72 input data channels with an equivalent data rate of 3.2 Gb/s. However if the system under test has 96 data channels with a data rate of 2 Gb/s for a bandwidth of 192 Gb/s (less than the instrument bandwidth of 230 Gb/s), the 2× mode is too slow (rate of 1.6 Gb/s is less than SUT rate of 2 Gb/s) and the 4× mode is not wide enough (only 72 input data channels where 96 are required). Therefore an intermediate mode between 2× and 4× may make the measurement instrument operate most efficiently.
Therefore what is desired is a non-standard demultiplex mode for a measurement instrument between standard, factor of two, demultiplex modes, such as a 3× mode between 2× and 4× modes.